Soft errors in integrated circuit devices result from high energy particles that pass through semiconductor devices. Soft errors are particularly problematic in DRAM and SRAM devices as they can cause the memory cell to flip, corrupting the stored data. Most computer systems deal with soft errors using single-bit error correction algorithms that use error correction words to identify errors and fix the corrupted data. However, as device densities and die sizes increase, and as memory widths move to ×8, ×16 and wider memory devices, the likelihood of multiple-bit errors increases. The single-bit error correction algorithms that are currently used may not be able to correct these multiple-bit errors, resulting in lost data and potentially causing system failure.
Accordingly, there is a need for a method and apparatus that reduce the occurrence of soft errors in memory cells. In addition, there is a need for a DRAM cell and a SRAM cell that have high soft error tolerance. The method and apparatus of the present invention meets the above needs.